Many electronic devices use a Phase Locked Loop (PLL) to generate or recover clock signal, generate carrier signals for radio transmission etc. The background of the invention is given with reference to the PLL 10 in FIG. 1. A conventional PLL block structure is showed. A VCO (voltage-controlled oscillator) 103 generates an output signal of frequency f0. The frequency f0 depends on a tuning voltage VT, a digital coarse tuning word CT (Coarse Tuning) and a natural frequency of the VCO 103 according to formula 1, where fN is the natural frequency, KCT is the coarse tuning gain and KV is the tuning voltage gain.f0=fN+KCT·CT+KV·VT  formula 1
The frequency f0 is divided by a division ratio N using a Divider 101. The frequency of the divider output may be denoted fdiv. The divider 101 output signal, which is a square wave signal, is compared with a reference clock by a PLL controller 102. The reference clock frequency may be denoted fref. The PLL controller 102 determines if f0 needs to be increased or decreased, and VT is adjusted accordingly. In steady state, the output frequency f0 is given by formula 2.f0=N·fref(steady state)  formula 2
VT has a limited range and can therefore only be used to adjust the output frequency to a certain extent. If fN, KCT or KV are unknown or vary, the tuning voltage may exceed its range. If a wide range of output frequencies (wide range of N) is desired, the tuning voltage may also exceed its range.
The coarse tuning signal CT is first used to roughly calibrate the output frequency. This usually needs to be done by an automatic calibration system that should be both accurate and fast.